1. Field of the Invention
The present invention relates to a method of forming a via hole during the process of manufacturing a semiconductor device.
2. Description of the Related Art
In the conventional art, via holes are formed in semiconductor devices by the method illustrated in FIGS. 1A through 1G. Namely, the sequence of processes in forming a via hole in the conventional art is as follows.
(1) As shown in FIG. 1A, a first SiO2 layer 2 is formed on a Si substrate 1.
(2) As shown in FIG. 1B, a first Al layer 3 is deposited by a sputtering method.
(3) As shown in FIG. 1C, a resist pattern 4 for forming a wiring pattern is formed on the first Al layer 3 by lithography.
(4) As shown in FIG. 1D, a first Al wiring 33 is formed by plasma etching.
(5) As shown in FIG. 1E, a second SiO2 layer 5 is formed as an interlayer dielectric layer.
(6) As shown in FIG. 1F, a resist pattern 6 for forming a via hole pattern is formed by lithography.
(7) As shown in FIG. 1G, a via hole 7 is formed by plasma etching.
However, in the conventional via hole forming methods, in cases in which the via hole is misaligned with respect to the wiring pattern when the via hole pattern is formed by lithography, not only is the second SiO2 layer 5 (which is to be removed by etching), but also the first SiO2 layer 2 is etched (see FIG. 1G). If the etching reaches the Si substrate 1 as shown in FIG. 2A, a short circuit will be formed between the first Al wiring 3 and the Si substrate 1 via a second Al layer 8 which is deposited thereafter. As a result, the problem that the semiconductor device will not function properly will arise.
In view of the aforementioned, an object of the present invention is to overcome the above-described drawbacks of the prior art. Namely, the present invention provides a method of forming a via hole in a semiconductor substrate in which, even if a via hole pattern is misaligned with respect to a wiring pattern during the time the via hole pattern is being formed by lithography, etching of the SiO2 layer will not proceed to the underlying Si substrate, and accordingly, no short circuit will be formed between the first wiring and the Si substrate via a second wiring layer which is deposited thereafter.
In order to achieve this object, a first aspect of the present invention is a method of manufacturing a semiconductor device comprising the steps of: forming a wiring pattern on a primary surface of a semiconductor substrate, the wiring pattern being formed by layering a conductive layer and a TiN layer; forming an oxide layer to cover the primary surface of the semiconductor substrate and the wiring pattern formed thereon; and exposing a portion of the upper portion surface of the wiring pattern by photolithography and etching, and forming an opening in a portion of the oxide layer, the opening extending from one portion of the upper portion surface of the wiring pattern and being within a predetermined distance from a side wall end of the wiring pattern.
In a second aspect of the present invention, in the first aspect, the compositional ratio by mole of nitrogen in the TiN layer is 1 or more.
A third aspect of the present invention is a method of manufacturing a semiconductor device comprising the steps of: forming a wiring pattern on a primary surface of a semiconductor substrate, the wiring pattern being formed by layering a conductive layer and a layer of material containing nitrogen; forming an oxide layer to cover the primary surface of the semiconductor substrate and the wiring pattern formed thereon; and exposing the upper portion surface of the conductive layer at a portion of the wiring pattern by photolithography and etching, and forming an opening in a portion of the oxide layer, the opening extending from one portion of the upper portion surface of the wiring pattern and being within a predetermined distance from a side wall end of the wiring pattern.
A fourth aspect of the present invention is a method of manufacturing a semiconductor device comprising the steps of: forming a wiring pattern on a primary surface of a semiconductor substrate by using a conductive layer; forming a spacer, which is formed by a layer of material containing nitrogen, on side walls of the wiring pattern; forming an oxide layer to cover the primary surface of the semiconductor substrate and the wiring pattern and spacer formed thereon; and exposing a portion of the upper portion surface of the wiring pattern by photolithography and etching, and forming an opening in a portion of the oxide layer, the opening extending from one portion of the upper portion surface of the wiring pattern and being within a predetermined distance from a side wall end of the wiring pattern.
A fifth aspect of the present invention is a method of manufacturing a semiconductor device comprising the steps of: forming a wiring pattern on a primary surface of a semiconductor substrate by using a conductive layer; forming a layer of material containing nitrogen to cover the primary surface of the semiconductor substrate and the wiring pattern formed thereon; forming an oxide layer on a layer of material containing nitrogen; and exposing a portion of the upper portion surface of the wiring pattern by photolithography and etching, and forming an opening in a portion of the oxide layer, the opening extending from one portion of the upper portion surface of the wiring pattern and being within a predetermined distance from a side wall end of the wiring pattern.
A sixth aspect of the present invention is a method of manufacturing a semiconductor device comprising the steps of: forming a layer of material containing nitrogen on a primary surface of a semiconductor substrate; forming a wiring pattern on the nitrogen layer by using a conductive layer; forming an oxide layer to cover a layer of material containing nitrogen and the wiring pattern formed thereon; and exposing a portion of the upper portion surface of the wiring pattern by photolithography and etching, and forming an opening in a portion of the oxide layer, the opening extending from one portion of the upper portion surface of the wiring pattern and being within a predetermined distance from a side wall end of the wiring pattern.
A seventh aspect of the present invention is a method of manufacturing a semiconductor device comprising the steps of: forming a wiring pattern on a primary surface of a semiconductor substrate by using a conductive layer; forming an organic silicon dioxide layer by rotatingly applying an organic silicon containing solution onto the primary surface of the semiconductor substrate and the wiring pattern formed thereon; forming an oxide layer on the organic silicon dioxide layer; and exposing a portion of the upper portion surface of the wiring pattern by photolithography and etching, and forming an opening in a portion of the oxide layer, the opening extending from one portion of the upper portion surface of the wiring pattern and being within a predetermined distance from a side wall end of the wiring pattern.
In an eighth aspect of the present invention, in the first aspect, in a case in which a planar pattern of the opening is a substantially circular pattern having a diameter of at least 0.3 xcexcm, the predetermined distance being no more than 0.15 xcexcm.
In a ninth aspect of the present invention, in the first aspect, in a case in which a planar pattern of the opening is a substantially circular pattern having a diameter of less than 0.3 xcexcm, the predetermined distance being no more than one-half of the diameter of the opening.
A tenth aspect of the present invention is a method of manufacturing a semiconductor device comprising the steps of: (a) forming a wiring pattern on a primary surface of a semiconductor substrate; (b) forming an etch resistant layer on the primary surface of the semiconductor substrate; (c) forming an electrically insulative layer covering the wiring layer; and (d) forming a via hole through the insulative layer to the wiring pattern, and if not to the wiring pattern, then to the etch resistant layer.
In an eleventh aspect of the present invention, in the tenth aspect, the etch resistant layer includes TiN.
In a twelfth aspect of the present invention, in the eleventh aspect, the compositional ratio by mole of N in the TiN, is at least 1.
In a thirteenth aspect of the present invention, in the eleventh aspect, the compositional ratio by mole of N in the TiN, is at least 1.2.
In a fourteenth aspect of the present invention, in the tenth aspect, the etch resistant layer includes SiN.
In a fifteenth aspect of the present invention, in the tenth aspect, the etch resistant layer is formed from an organic spin on glass material.
In a sixteenth aspect of the present invention, in the tenth aspect, the etch resistant layer is formed over the wiring pattern.
In a seventeenth aspect of the present invention, in the tenth aspect, the step of forming a via hole exposes a portion of the etch resistant layer, and further including the step of removing at least a part of the exposed portion of the etch resistant layer.
In an eighteenth aspect of the present invention, the method of the tenth aspect further includes the step of removing a portion of the etch resistant layer, prior to forming an electrically insulative layer covering the wiring layer.
In a nineteenth aspect of the present invention, in the method of the eighteenth aspect, the wiring pattern covers portions of the silicon substrate and the step of removing a portion of the etch resistant layer, includes removing the portion of the etch resistant layer sufficient to expose the wiring pattern therebeneath, with the remainder of the etch resistant layer substantially covering the silicon substrate.
In a twentieth aspect of the present invention, in the tenth aspect, the etch resistant layer is formed over the silicon substrate, and the wiring pattern is formed over the etch resistant layer.